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Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation

Transactional Memory (TM) is a programming abstraction that aims to ease parallel programming in shared-memory architectures. Both Hardware (HTM) and Software Transactional Memory (STM) implementations have been extensively studied in the literature. Modern approaches seek to combine both HTM and STM to better exploit performance. In particular, Phased TMs (PhTMs) systems execute transactions in phases, not allowing both hardware and software transactions to run concurrently to avoid coordination overheads. The main challenge in designing PhTM systems is to dynamically choose a proper execution mode. Usually, a transition mechanism is developed based on metrics such as transaction size and abort rates to guide the phase migration. However, the tuning of such metrics is not an easy task, since it may lead to over-fitting and poor performance for the general case. This paper advances state-of-the-art research on PhTM by proposing a different approach to phase selection: the use of commit throughput and cache simulation to mimic the behavior of HTM storage constraints while in STM mode. When compared to previous work, this approach leads to a simpler and more efficient mechanism to assess the state of the execution modes in run time. Experimental results using STAMP and two graph processing applications show how the CTTM mechanism is able to outperform a state-of-the-art Phased TM runtime (PhTM*) with speedups of up to 5x.
 
 
C. M. Morales, B. Honorio, A. Baldassin and G. Araujo, “Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation,” 2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2021, pp. 44-53, doi: 10.1109/SBAC-PAD53543.2021.00016.
 
 
https://ieeexplore.ieee.org/document/9651601

 

 
 
 

 

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